http://arxiv.org/abs/2002.02534
We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the conversion of a trained model into an FPGA firmware through an automatic highlevel-synthesis conversion. Thanks to its full on-chip implementation, hls4ml allows performance of inference of Boosted Decision Tree models with extremely low latency. A benchmark model achieving near state of the art classification performance is implemented on an FPGA with 60 ns inference latency, using 8% of the Look Up Tables of the target device. This solution is compatible with the needs of fast real-time processing such as the L1 trigger system of a typical collider experiment.
S. Summers, G. Guglielmo, J. Duarte, et. al.
Mon, 10 Feb 20
21/59
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